Samsung Electronics Expand Industry’s First 12-Layer 3D-TSV Chip Packaging Technology

A world leader in advanced semiconductor innovation, today reported that it has built up the industry’ initial 12-layer 3D-TSV (Through Silicon Via) innovation.

Cross-segment of 8-layer versus Samsung’s new 12-layer 3D-TSV Chip Packaging structure (Graphic: Business Wire)

Samsung’s new development is viewed as one of the most testing bundling advancements for large scale manufacturing of superior chips, as it requires pinpoint precision to vertically interconnect 12 DRAM chips through a three-dimensional configuration of more than 60,000 TSV holes, every one of which is one-twentieth the thickness of a solitary strand of human hair.

The thickness of the bundle (720㎛) continues as before as present 8-layer High Bandwidth Memory-2 (HBM2) items, which is a generous progression in segment design. This will enable clients to discharge people to come, high-limit items with better limit without changing their framework setup designs.

What’s more, the 3D packaging innovation additionally includes a shorter information transmission time between chips than the as of now existing wire bonding innovation, bringing about fundamentally quicker speed and lower control utilization.

“Packaging technology that secures all of the intricacies of ultra-performance memory is becoming tremendously important, with the wide variety of new-age applications, such as artificial intelligence (AI) and High Power Computing (HPC),” said Hong-Joo Baek, executive VP of TSP (Test and System Package) at Samsung Electronics. “As Moore’s law scaling reaches its limit, the role of 3D-TSV technology is expected to become even more critical. We want to be at the forefront of this state-of-the-art chip packaging technology.”

Depending on its 12-layer 3D-TSV innovation, Samsung will offer the most noteworthy DRAM execution for applications that are information concentrated and amazingly fast.

Likewise, by expanding the quantity of stacked layers from eight to 12, Samsung will before long have the option to mass produce 24-gigabyte (GB)* High Bandwidth Memory, which gives multiple times the limit of 8GB high transfer speed memory available today.

Samsung will have the option to meet the quickly developing business sector interest for high-limit HBM arrangements with its bleeding edge 12-layer 3D TSV innovation and it wants to harden its leadership in the top notch semiconductor market.

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