Samsung Electronics Expand Industry’s First 12-Layer 3D-TSV Chip Packaging Technology

A world leader in advanced semiconductor innovation, today reported that it has built up the industry’ initial 12-layer 3D-TSV (Through Silicon Via) innovation. Cross-segment of 8-layer versus Samsung’s new 12-layer 3D-TSV Chip Packaging structure (Graphic: Business Wire) Samsung’s new development is viewed as one of the most testing bundling advancements for large scale manufacturing of superior chips, as it requires pinpoint precision to vertically interconnect 12 DRAM chips through a three-dimensional configuration of more than 60,000 TSV holes, every one of which is one-twentieth the thickness of a solitary strand…

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